1. Field of the Invention
This invention relates to a semiconductor device, and particularly to a layout of input/output cells employed in an ASIC (Application Specific Integrated Circuit) such as a gate array, an embedded array or the like.
2. Description of the Related Art
A semiconductor device, particularly an ASIC, makes various implementation demands according to the purposes of users in a short time, in terms of the time required for the development and manufacturing process. Since the ASIC is fabricated according to the purposes of the users, there is a tendency to use it in a wide variety of products.
The semiconductor devices are formed as the separate products according to the number of pads as follows. Pads are respectively placed at predetermined intervals according to the number of the pads therein. With respect to input/output cells having elements or devices for respectively forming input/output circuits in accordance with the pads, the widths (corresponding to lengths extending in the direction in which the pads are placed) are respectively determined according to the number of the pads and layout intervals between the respective pads. Therefore, even input/output cells that differ with regards to the size of the input/output cell forming region are prepared in the same circuit configuration in accordance with the number of the pads.
Thus, since even devices that differ with regards to the size of the input/output cell forming region are prepared, their fabrication and development are performed correspondingly and their fabrication and development costs are involved. Therefore, the conventional semiconductor devices do not always satisfy a user's demands with ease in terms of time and a reduction in cost.
With a multi-pin configuration of a semiconductor device, it becomes increasingly difficult to place a plurality of pads within a limited pad placement region in a row. As a countermeasure against this difficulty, a so-called zigzag pad arrangement is known in which pads are placed alternately closer to and further from input/output cells.
In this case, wires or interconnections for respectively connecting between the pads that are placed farther from the input/output cell side and the input/output cells become narrow in width, so that the amount of current allowable for each interconnection is reduced. Thus, since the amount of allowable current in this case becomes less than the amount of current allowable for the pads that are placed close to the input/output cell side, limitations are imposed on signals for objects which utilize the pads that are placed farther from the input/output cell side.